As IC technology advances and device dimensions decrease while circuit speeds increase, packaging and diagnostic techniques have advanced accordingly. Methods for modification and editing of circuits and devices have undergone dramatic changes, due in part to two factors. The stacking of increasingly large numbers of metal layers has limited the access to lower metal layers from the wafer frontside. In addition, the widespread use of flipchip mounting, wherein the IC is mounted face down on a packaging substrate, leaving only the backside of the chip exposed, precludes front side access to the chip. As a result of these aforementioned factors, backside signal measurement, editing, and modification of IC's has become increasingly important, using such techniques as Focused Ion Beam (FIB). The use of FIB in backside editing and repair of IC's is described by C. G. Talbot et al in commonly owned U.S. Pat. No. 6,518,571, issued Feb. 11, 2003, and by T. Lundquist et al in commonly owned U.S. patent application Ser. No. 09/738,826, filed on Dec. 15, 2000, both of which are hereby incorporated in their entirety by reference. The technique includes: 1) the global thinning of the die, 2) the optional cutting of a coarse trench (by methods such as Laser Chemical Etching or FIB), 3) milling of a smaller trench within the LCE trench to within one to a few microns of the active diffusion regions (by chemically assisted FIB), 4) FIB sputter removal or fine chemically assisted FIB milling between active diffusion regions or active devices to provide access to one or more circuit elements, and finally 5) probing, cutting, depositing, or connecting signal paths as required.
Precise endpoint control over the milling of the small trench is critical to avoid damaging of active diffusion regions. Various methods of trench endpointing have been reported in the literature. By way of example, Winer et al, in U.S. Pat. No. 5,948,217 disclose a method of endpointing which is sensitive to changes in diffusion region doping chemistry, but which requires biasing of diffused regions such as n-wells with respect to the substrate.
A challenge in backside editing is navigation, i.e., locating the exact circuit node where a modification or repair is needed. To effectively and accurately access the circuit elements to be modified, both the milling of the small trench and the fine FIB milling must be accurately positioned and registered with respect to the circuit design (CAD) and circuit elements. Various techniques have been used to create a backside image, which can be matched to the CAD layout of the chip.
A prior method for registration is IR imaging through the silicon. The IR light can pass through silicon, and optical information about the location on the chip, as well as about remaining thickness of silicon (i.e., endpoint information) is provided. This method is described in previously cited U.S. Pat. No. 6,518,571, and by E. Le Roy et al in commonly owned U.S. patent application Ser. No. 10/161,272 filed on May 30, 2002. An IR imaging and navigation system has been combined with FIB in an apparatus called IDS OptiFIB, made by NPTest, LLC. The resolution of IR imaging is limited to its wavelength, but use of an imaging process algorithm should improve corresponding CAD alignment accuracy to a fraction of one wavelength. Use of the IDS OptiFIB for CAD alignment is described in commonly owned U.S. patent application Ser. No. 10/159,527 by M. Sengupta et al, filed May 30, 2001, which is hereby incorporated in its entirety by reference.
A method known as voltage contrast, which does not utilize IR and which has been used in front-side imaging, has been recently applied in backside navigation, as described in the commonly owned U.S. patent application Ser. No. 10/274,431 by C. C. Tsao et al, filed Oct. 17, 2002, which is hereby incorporated in its entirety by reference. This method includes the biasing of n-well implanted regions with respect to the p-substrate, and shows a clear backside FIB image of the n-well regions which can be used for registration to the CAD design. However, this prior method is not effective in imaging non-biased regions. Additionally, operational complexity is introduced by this method, since a special socket for each particular device and the interconnect board to the electrical bias is required to provide the bias, and an increased knowledge level is required to know which pins should be biased relative to which others. An alternative method for registering the CAD to the FIB image which did not require biasing and which could distinguish between surface and buried material regions, as well as a method to ensure accurate endpoint detection in the small trench milling, would be advantageous in through the substrate probing and circuit modification and other modifications for flip-chip mounted IC's and properly prepared wire-bonded IC's, and could additionally be utilized in obtaining vertical doping profiles for n-well characterization for failure analysis, and possibly for p-well characterization.